1. Field of the Invention
The present invention relates to methods for forming low-k dielectric films on semiconductor wafers. More particularly, the present invention relates to methods for forming low-k dielectric layers with improved structural integrity during the manufacture of semiconductor integrated circuits.
2. Description of the Related Art
As integrated circuits become smaller, it becomes more desirable to reduce interconnection delays through the selection of materials used in the interconnects and associated dielectric layers. The propagation delays through the interconnects are proportional to the resistance of the interconnects and the capacitance offered by the dielectric. In fact, as integrated devices become smaller, the resistance capacitance (RC) delay time of signal propagation along interconnects becomes the dominant factor limiting overall chip speed. In order to improve the interconnect performance, higher conductance and lower capacitance is required of the interconnects. In order to accommodate these objectives, the trend has been towards the use of copper for interconnects and damascene methods for forming the interconnects in low-k layers.
For conductors, copper has gained favor in the industry because of its many advantages, including its low resistance. In such processes, conducting metal (e.g., copper) is inlaid into trench and via structures of insulating material (e.g., low-k dielectric materials). CMP (Chemical Mechanical Polishing) is used to remove conducting metal (e.g., copper) in single or dual damascene processes. With the advent of copper technology, resistance has been minimized and attention has been focused on reducing capacitance.
One method conventionally used to reduce capacitance is to reduce the average dielectric constant k of the thin insulating films surrounding interconnects through the introduction of porosity. The dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.1. A number of dielectric materials have been developed having a dielectric constant lower than that of SiO2. These are generally referred to as low-k materials and several of these layers may appear on a wafer. That is, integrated circuits are often made up of many interconnect levels to connect the various devices of the circuit. The low-k dielectric materials are used to electrically isolate the different levels of metallization as well as isolate the metal interconnects on the same level. Thus, a semiconductor device may include several low-k layers disposed on top of each other.
Introduction of porosity to reduce the dielectric constant can result in a reduction of strength and structural stability. That is, the lack of mechanical rigidity of the composite low-k and metal interconnect materials causes delamination of the low-k to low-k layers and low-k to copper layers a well as cracking of the bulk material. The mechanical strength of low-k films is considerably less than that of traditional silicon dioxide. That is, as the dielectric constants reach lower values, the structural integrity of the films decrease. While not wishing to be bound by any particular theory, it is believed that to decrease the k value of the film, porosity must be introduced.
For example, the k value of SiO2 is approximately 4.1 whereas the k value of air is defined as 1. By adding different materials to the base SiO2 layer, lower k values can be obtained. Unfortunately a point is quickly reached where the only way to effectively lower the k value is to introduce porosity (effectively air) into the film itself. This feature causes the significant structural integrity problem observed in the film.
This compromised mechanical strength of the low-k film significantly increases the likelihood of damage to the structure of the low-k copper dual damascene system during conventional chemical mechanical polishing (CMP). The films tend to crack, shear and otherwise cause defects that render semiconductor devices useless. That is, while the wafers are subjected to chemical mechanical polishing (CMP), shear stresses and other mechanical damage may cause defects that cause the devices to fail. This problem is compounded with integration of higher levels of metallization.
This presents an ever-challenging task for CMP and developers of dielectric films. For example, CMP vendors are working on new pad materials and slurry solutions to optimize planarization with a much lower down force, but this approach has its limitations. Alternate methods of planarization are in their infancy. One current solution is to compromise the k-value for the added mechanical strength. However, for smaller technology nodes, the k values for the inter metal dielectric (IMD) need to be lowered to reduce the RC delay.
The low-k dielectric materials used to electrically isolate the different levels of metallization in a silicon substrate present other mechanical problems as well. The electrical connections between different interconnection levels are made through the use of metallized vias. Thus, a semiconductor device may include several low-k layers attached on top of each other, each low-k layer to low-k layer interface offering a potential delamination problem.
Moreover, low-k materials offer poor resistance to compression. This is significant in packaging of dies. For example, once the integrated circuits on the wafer are completed, i.e., layering and patterning are implemented, the wafer is conventionally sliced into sections known as die. The die are conventionally packaged to facilitate electrical connections to external circuitry. Generally, in semiconductor manufacturing, an individual semiconductor die is mounted to a substrate and then sealed by an encapsulant or by a molding operation. After mounting, electrical connection from the die to the package bonding pads may be completed using wire bonding techniques, for example. Typically, after packaging, the packaged die is placed flat on the printed circuit board (“PCB”) and electrical connections made to traces or landings on the printed circuit board, for example by wire bonding, solder ball bonding, or other conventional methods.
Any of these connection methods may place large stress forces on the substrate. For example, wire bonding requires that a large compressive force be placed on the bonding pad as heat is generated to “weld” the bonding wire to the pad. In using solder balls for connections to external circuitry, the ball bonding process window is directly related to the mechanical strength of the composite films that make up the bed and affects the ability to route circuitry under the ball bond pad. Often, however, the low-k layers underneath the bonding pad may comprise as may as 10 or more layers. The poor mechanical strength of the low-k material under the bonding pad thus may affect the ability to route circuitry under the ball bond pad. That is, interconnect circuitry placed under the bond pad may be damaged from the forces imposed during wire bonding, such as by crushing the underlying dielectric layers, or similarly damaged from other electrical connection methods. The poor mechanical properties of the low k film affect the overall reliability of the chip and the types of packages that can be used for the chip.
Accordingly, it is desirable to provide improved methods for increasing the structural integrity of the low-k films without appreciably affecting the low k values of the dielectric film